DVCon U.S. 2023 Announces Stuart Sutherland Best Paper &

GAINESVILLE, Fla., March 08, 2023 (GLOBE NEWSWIRE) — The 2023 Design and Verification Conference and Exhibition US (DVCon US), sponsored by Accellera Systems Initiative (Accellera), held its 35th annual event in San Jose, California last week. completed . The winners of the Best Paper and Best Poster 2023, voted for by the participants, were announced during a reception in the exhibition hall on March 1st.

The participants came from 35 countries and represented about 275 companies, of which 323 attended the conference and exhibition for the first time. The total attendance for DVCon US 2023 was approximately 850.

“We were thrilled to be attending in person again this year,” said Vanessa Cooper, General Chair of DVCon US 2023. “The energy and excitement of attendees was evident throughout the conference, particularly during the new Poster Ninja Warrior Session. We had the top four poster presenters compete in front of a standing room only audience with lively audience participation, creating an atmosphere of excitement and fun for the participants. The exhibition hall was also busy during the receptions, and many colleagues met face to face for the first time since 2020. Our technical sessions were also very well attended, with many topics for attendees to choose from. We are very proud that DVCon continues to be a vital resource for the practicing design and verification engineer and that what they learn will help them succeed in their current and future projects.”

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The Stuart Sutherland Best Paper Presentation award, voted for by the conference attendees, went to Chuck McClish, Microchip Technology Inc. for “Take AIM! Introduction to the Analog Information Model.” Runners-up Jun Yan and Josh Baylor, Renesas Electronics, presented “Automated Modeling Testbench Methodology Tested with four Types of PLL Models”. Rob Donnelly and Josh Geden of the NASA Jet Propulsion Laboratory took third place for their article “Regvue: Modern Register Documentation”.

The top award for Best Poster went to Robert Martin, Alan Curtis and Qingwei Zhou, Intel and Gopinath Narasimhan, Synopsys for “Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus for IP Validation”. Eldhose PM, Suraj Shetty, Sagar Jayakrishnan, Kuntal Pandya and Parag S. Lonkar, Samsung received second place for “An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs”. Woojoo Kim, Kunhyuk Kang and Seonil Brian Choi, Samsung took third place for “A Study on Virtual Prototyping based Design Verification Methodology”.

Highlights of the week:

  • The conference kicked off Monday with Accellera Day with a morning tutorial on Portable Test and Stimulus Standard (PSS) user experiences and nine workshops throughout the day.
  • Bob Smith, Director of the SEMI/ESD Alliance, presented “The CHIPs Act and its Impact on the Design and Verification Industry” during Monday’s lunch.
  • More than 200 attended the keynote speech “What do agriculture, steel and space have in common?” on Tuesday. Presented by Dirk Didascalou, CTO Siemens Digital Industries. Dirk focused on the digital transformation in the electronics industry and the need for companies to move away from an “ego” system and work towards an ecosystem together.
  • There were two panels on Wednesday: “Systems are Evolving. Is verification keeping up?” moderated by Bernard Murphy, SemiWiki. and “AI-ML Algorithms are Transforming Verification: Separating Hype from Reality,” moderated by Shankar Hemmady, CEO, Blue Horizons. Both sessions were well attended and gave the audience the opportunity to ask questions of the panellists.
  • The Accellera-sponsored luncheon on Wednesday saw the presentation of the Accellera 2023 Technical Excellence Award, which was presented posthumously to Phil Moorby, inventor of Verilog HDL. Some of his close colleagues shared stories and photos from their time with Phil, giving attendees a glimpse of the significant impact he’s had on the industry. The lunch ended with Mark Himelstein, CTO of RISC-V International, who gave a presentation on RISC-V Everywhere.
  • New to the program this year was the Poster Ninja Warrior Session, where the winners of the Stuart Sutherland Best Poster Award were determined. The top four posters competed in front of a standing room-only audience to see who would take the top honor. Audience participation helped decide the winners.
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The DVCon steering committee appreciates any feedback on the conference. DVCon US attendees completed a survey and are asked to provide input and feedback on how we can improve and continue to make DVCon the industry’s must-attend conference for design and verification engineers.

Make a note of the appointment: DVCon US 2024 will be held March 4-7 at the DoubleTree Hotel in San Jose, California. Tom Fitzpatrick is appointed General Chair of DVCon US 2024.

About DVCon
DVCon is the leading conference for discussing the functional design and verification of electronic systems. DVCon is sponsored by the Accellera Systems Initiative, an independent, not-for-profit organization dedicated to developing design and verification standards needed by systems, semiconductor, intellectual property (IP), and electronic design automation (EDA) companies. For more information about Accellera, visit More information about DVCon US can be found here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or use #dvcon_us to comment.

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